(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of integrating partial silicide and self-aligned contact processes in the fabrication of integrated circuits.
(2) Description of the Prior Art
In deep submicron ULSI technology, low voltage applications and low threshold voltages are required to decrease power consumption and to increase circuit speed. For ease of fabrication, n-doped polysilicon gates have been used for both n-channel and p-channel devices. These buried channel type PMOS devices are quite susceptible to short channel effects. Great improvement can be made if both PMOS and NMOS devices are surface channel types. In the dual gate surface channel CMOS process, where an NMOS and a PMOS gate come together, a silicide layer is formed thereover to reduce resistance and to ensure ohmic contact. Salicide or polycide technology is used in the dual gate process.
In silicidation, a refractory metal layer is deposited and then annealed. The underlying silicon reacts with the refractory metal layer to produce a silicide overlying the gate electrode. The silicided gate has lower resistance than non-silicided regions, especially in smaller geometries, and hence, higher circuit performance.
In some processes, such as the self-aligned contact process, it is difficult to incorporate the salicide or polycide gate process because of thermal cycling or auto-doping concerns. That is, if the silicide is formed just after gate definition, the subsequent thermal cycles for driving in LDD and source/drain regions and forming spacers, for example, will cause auto-doping of the gate through the silicide layer or will degrade the resistance of the silicide. It is desired to introduce a partial silicide process to connect a CMOS surface channel gate into a SAC process.
Silicidation has been widely used in the art. Silicidation techniques and self-aligned contacts are discussed in Silicon Processing for the VLSI Era, Vol. 2, by S. Wolf, Lattice Press, Sunset Beach, Calif., c. 1990, pp. 144-149 and in ULSI Technology, by C. Y. Chang and S. M. Sze, McGraw-Hill, New York, N.Y., c. 1996, pp.397-402 and 487-488. U.S. Pat. No. 5,668,035 to Fang et al and U.S. Pat. No.5,837,601 to Matsumoto teach dual gate processes. U.S. Pat. No. 5,550,079 to Lin teaches forming a nitrogen-containing silicide shunt over dual gate CMOS devices.